1. Technical Field
This disclosure generally relates to making integrated circuit packages with “handle wafers,” and more particularly, to making discrete electrical components, such as capacitors, within the handle wafers of such packages.
2. Related Art
The “wafer level” or “wafer scale” production of integrated circuit (IC) packages has proliferated in recent years, due primarily to the economies of scale that such production techniques afford, together with the concomitant reduction in size and cost of the resulting packages.
Examples of such IC packages and methods for making them can be found in, e.g., commonly owned U.S. patent application Ser. No. 14/214,365 by H. Shen, et al., filed Mar. 14, 2014, and entitled “Integrated Circuits Protected by Substrates with Cavities, and Methods of Manufacture,” the entire disclosure of which is incorporated herein by reference.
In one of only many possible embodiments of such packages, the packages, which are cut, or “singulated” from a sandwich of two wafers containing a number of similar packages, can include a portion of a wiring substrate wafer, sometimes referred to as an “interposer wafer,” having an upper surface upon which are disposed one or more semiconductor dies or chips (which may be packaged or unpackaged), each containing one or more integrated circuits (ICs). The interposer can contain a pattern of electroconductive traces, e.g., in the form of a “redistribution layer” (RDL), to which the ICs are variously electroconductively connected. The interposer can also contain discrete electrical components, such as “trench capacitors,” that are formed either on its surface or within its thickness.
The IC package can further include a portion of a “handle wafer” that contains one or more cavities in its lower surface. The lower surface of the handle wafer can be bonded to the upper surface of the interposer such that the semiconductor dies are disposed protectively within the cavities of the handle wafer. The handle wafer thus provides not only a protective environment for the dies, but also a convenient mechanism for “handling” interposer wafers that are relatively thin, say, on the order of about 5×10−6 meters (5 μm) thick, or for holding interposer wafers during a thinning operation, e.g., by chemical mechanical planarization (CMP).
However, a practical problem arises when the interposer wafer of such packages is made substantially thin, in that this limits the vertical height of the discrete electrical components, such as capacitors, that can be built into the thickness of the interposer, and hence, their maximum surface area or capacitance.
Accordingly, a long felt but as yet unsatisfied need exists for methods and apparatus that overcome the foregoing and other problems of the prior art.